Multi-threading of arithmetic processing devices (i.e., processors or central processing units (CPUs)), in which each of the processors executes a plurality of threads, is proceeding. The multi-threading needs the efficient processing of cache memories (hereinafter, simply abbreviated as “caches”). In particular, instruction caches are needed to efficiently process the instruction fetch requests of respective threads when reading the respective instructions of the plurality of threads from memories.
For example, an instruction cache needs to process instruction fetches based on the order of instruction fetch requests inside threads but is allowed to the process instruction fetches regardless of the order of the instruction fetch requests between the threads.
When a plurality of instruction caches are provided corresponding to the multi-threading, the respective instruction caches are allowed to process the instruction fetch requests of respective threads in the same way as single threads. In addition, it has been proposed that one instruction cache control unit is shared between a plurality of threads and that a request port used to retain instruction fetch requests output from an instruction control unit and a wait port used to manage instruction fetch requests aborted due to their cache errors are provided for each of the plurality of threads.
A configuration in which an instruction cache is provided corresponding to the multi-threading is described in the Patent Literatures, International Publication Pamphlet No. WO2008/155826 and Japanese National Publication of International Patent Application No. 2011-511378.